The semiconductor industry is on an ongoing quest to integrate more functionality into a smaller form factor with increased performance, lower power and reduced cost. Traditionally, only two-dimensional planes were used for these smaller form factors: through conventional CMOS scaling, multiple IP cores in a single die (System-on-Chip, SoC), multiple dies in a single package (Multi-Chip Package, MCP) and multiple ICs on a printed Circuit Board (PCB). More recently, also the third, vertical dimension started to become exploited: System-in-Package (SiP), in which multiple naked dies are vertically stacked in a single IC package, and interconnected by means of wire-bonds to the substrate; and Package-on-Package (PoP), in which multiple packaged chips are vertically stacked.
Three-dimensional (3D) stacking of chips promises higher transistor densities and smaller footprints of electronic products. The latest evolution in this list of innovations is the so-called three-dimensional stacked IC (3D-SIC); a single package containing a vertical stack of naked dies which are interconnected by means of inter-die interconnections, optionally including through-substrate-vias (TSVs).
Semiconductor manufacturing processes are defect-prone and hence all ICs need to be tested for manufacturing defects. Stacked ICs are no exception to this. Hence these new inter-die connected 3D-SICs need to be tested for manufacturing defects, in order to guarantee sufficient outgoing product quality to a customer. Chip stacks should be delivered fault free as much as possible. In 3D chip stacking, the inter-die interconnections carry all interconnect signals between two dies, and hence are quite critical for functional operation of the chip. Both the inter-die interconnection manufacturing process, as well as the bonding process are delicate, and hence the inter-die interconnects are prone to defects, such as for example opens, shorts, delay defects, or resistance issues.
Common static fault models for interconnects are hard opens and shorts. They can be tested with a static (DC) test using wrappers. Dedicated test pattern generation tools are available for generating the appropriate test patterns. However, inter-die interconnects can also exhibit other defects which are problematic and are not covered by existing designed-for-testing or DfT solutions.
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